Exploiting the Performance Benefits of Storage Class Memory for HPC and HPDA Workflows

Michele Weiland; Adrian Jackson; Nick Johnson; Mark Parsons

doi:10.14529/jsfi180105

Authors

Michele Weiland The University of Edinburgh
Adrian Jackson The University of Edinburgh
Nick Johnson The University of Edinburgh
Mark Parsons The University of Edinburgh

DOI:

https://doi.org/10.14529/jsfi180105

Abstract

Byte-addressable storage class memory (SCM) is an upcoming technology that will transform the memory and storage hierarchy of HPC systems by dramatically reducing the latency gap between DRAM and persistent storage. In this paper, we discuss general SCM characteristics, including the different hardware configurations and data access mechanisms SCM is likely to provide. We outline the performance challenges I/O requirements place on traditional scientific workflows and present how data access through SCM can have a beneficial impact on the performance of such workflows, in particular those with large scale data dependencies. We describe the system software components that are required to enabled workflow and data aware resource allocation scheduling in order to optimise both system throughput and time to solution for individual applications; these include a data scheduler and data movers. We also present an illustration of the performance improvement potential of the technology, based on initial workflow performance benchmarks with I/O dependencies.

References

Daley, C., Ghoshal, D., Lockwood, G., Dosanjh, S., Ramakrishnan, L., Wright, N.: Performance Characterization of Scientific Workflows for the Optimal Use of Burst Buffers. Future Generation Computer Systems (2017). DOI: 10.1016/j.future.2017.12.022

Deelman, E., Peterka, T., Altintas, I., Carothers, C.D., van Dam, K.K., Moreland, K., Parashar, M., Ramakrishnan, L., Taufer, M., Vetter, J.: The Future of Scientific Workflows. The International Journal of High Performance Computing Applications 32(1), 159–175 (2018). DOI: 10.1177/1094342017704893

Hady, F.T., Foong, A., Veal, B., Williams, D.: Platform Storage Performance with 3D XPoint Technology. Proceedings of the IEEE 105(9), 1822–1833 (Sept 2017). DOI: 10.1109/JPROC.2017.2731776

Herbein, S., Ahn, D.H., Lipari, D., Scogland, T.R., Stearman, M., Grondona, M., Gar- lick, J., Springmeyer, B., Taufer, M.: Scalable I/O-Aware Job Scheduling for Burst Buffer Enabled HPC Clusters. In: Proceedings of the 25th ACM International Symposium on High- Performance Parallel and Distributed Computing. pp. 69–80. HPDC ’16, ACM, New York, NY, USA (2016). DOI: 10.1145/2907294.2907316

Jette, M.A., Yoo, A.B., Grondona, M.: SLURM: Simple Linux Utility for Resource Management. In: In Lecture Notes in Computer Science: Proceedings of Job Scheduling Strategies for Parallel Processing (JSSPP) 2003. pp. 44–60. Springer-Verlag (2002)

Joydeep, R., Varghese, G., Inder M., S., Jeffrey R., W.: Intel Patent on Multi-Level Memory Configuration for Non-Volatile Memory Technology. https://www.google.com/patents/ US20150178204 (2013), Accessed: 2018-04-11

Rodrigo, G.P., Elmroth, E., O ̈stberg, P.O., Ramakrishnan, L.: Enabling Workflow-Aware Scheduling on HPC Systems. In: Proceedings of the 26th International Symposium on High-Performance Parallel and Distributed Computing. pp. 3–14. HPDC ’17, ACM, New York, NY, USA (2017)

Rudoff, A.: Persistent Memory Programming. http://pmem.io (2017). DOI: 10.1145/3078597.3078604. Accessed: 2018-04-11

Rudoff, A.: Persistent Memory: The Value to HPC and the Challenges. In: Proceedings of the Workshop on Memory Centric Programming for HPC. pp. 7–10. MCHPC’17, ACM, New York, NY, USA (2017). DOI: 10.1145/3145617.3158213

Sunny, G.: Getting Ready for Intel Xeon Phi Processor Product Family. https:// software.intel.com/en-us/articles/getting-ready-for-KNL (2017), Accessed: 2018-04-11